Stacked multi-die packages with impedance control

ABSTRACT

A microelectronic assembly may include microelectronic devices arranged in a stack and having device contacts exposed at respective front surfaces. Signal conductors having substantial portions extending above the front surface of the respective microelectronic devices connect the device contacts with signal contacts of an underlying interconnection element. A rear surface of a microelectronic device of the stack overlying an adjacent microelectronic device of the stack is spaced a predetermined distance above and extends at least generally parallel to the substantial portions of the signal conductors connected to the adjacent device, such that a desired impedance may be achieved for the signal conductors connected to the adjacent device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No. 12/883,612, filed on Sep. 16, 2010, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

Microelectronic chips are typically flat bodies with oppositely facing, generally planar front and rear surfaces with edges extending between these surfaces. Chips generally have contacts, sometimes also referred to as pads or bond pads, on the front surface which are electrically connected to the circuits within the chip. Chips are typically packaged by enclosing them with a suitable material to form microelectronic packages having terminals that are electrically connected to the chip contacts. The package may then be connected to test equipment to determine whether the packaged device conforms to a desired performance standard. Once tested, the package may be connected to a larger circuit (e.g. a circuit in an electronic product such as a computer or a cell phone) by connecting the package terminals to matching lands on a printed circuit board (PCB) by a suitable connection method such as soldering.

Microelectronic packages may be fabricated at the wafer level; that is, the enclosure, terminations and other features that constitute the package, are fabricated while the chips, or die, are still in a wafer form. After the die have been formed, the wafer is subject to a number of additional process steps to form the package structure on the wafer, and the wafer is then diced to free the individually packaged die. Wafer level processing can be an efficient fabrication method because the footprint of each die package may be made identical, or nearly identical, to the size of the die itself, resulting in very efficient utilization of area on the printed circuit board to which the packaged die is attached.

A common technique for forming electrically conductive connections between a microelectronic chip and one or more other electronic components is through wire-bonding. Conventionally, a wirebonding tool attaches the end of a wire to a pad on a microelectronic chip using thermal and/or ultrasonic energy and then loops the wire to a contact on the other electronic component and forms a second bond thereto using thermal and/or ultrasonic forces.

In microelectronic assemblies that include wire-bonds extending from the microelectronic chip to another electronic component, electromagnetic transmissions along the wire can extend into space surrounding the wire, inducing currents in nearby conductors and causing unwanted radiation and detuning of the line. Wire-bonds generally are also subject to self-inductances and are subject to external noise (e.g. from nearby electronic components). In the end, this creates electrical impedance problems. These problems can become more serious as the pitch between contacts on microelectronic chips and other electronic components becomes smaller, as the chips operate at higher frequencies, and as the use of multiple raw pads becomes more common.

SUMMARY OF THE INVENTION

In accordance with an embodiment of the invention, a microelectronic assembly may include a plurality of microelectronic devices arranged to form a stack of microelectronic devices. Adjacent first and second microelectronic devices in the stack each may have device contacts exposed at a front surface, and have a rear surface remote from the front surface. The assembly further may include an interconnection element underlying the second microelectronic device, the interconnection element having a plurality of signal contacts. First and second signal conductors respectively may connect the device contacts of the first and second devices with the signal contacts. The first and second signal conductors may have substantial portions extending above the front surfaces of the respective first and second microelectronic devices. The rear surface of the first microelectronic device may be spaced a predetermined first distance above and extend at least generally parallel to the substantial portions of the second signal conductors, such that a desired impedance is achieved for the second signal conductors.

In accordance with another embodiment of the invention, a method of fabricating a microelectronic assembly may include arranging a plurality of microelectronic devices in a stack including a first microelectronic device mounted above an adjacent second microelectronic device. The first and second microelectronic devices in the stack may have device contacts exposed at a front surface, and have a rear surface remote from the front surface. The method further may include connecting the device contacts of the first and second devices with signal contacts of an interconnection element, which underlies the second device, using respective first and second signal conductors. The second signal conductors may be connected to the signal contacts before the first signal conductors are connected to the signal contacts. The first and second signal conductors may have substantial portions extending above the front surfaces of the respective first and second microelectronic devices. The rear surface of the first microelectronic device may be spaced a predetermined first distance above and extend at least generally parallel to the substantial portions of the second signal conductors, such that a desired impedance is achieved for the second signal conductors.

In accordance with another embodiment of the invention, a method of fabricating a microelectronic assembly may include arranging a plurality of microelectronic devices in a stack over an interconnection element. Adjacent first and second microelectronic devices in the stack may have device contacts exposed at a front surface, and have a rear surface remote from the front surface, and the interconnection element may underlie the second microelectronic device. The device contacts of the first and second devices may be connected with signal contacts of the interconnection element by respective first and second signal conductors, where the second signal conductors are connected to the signal contacts before the first signal conductors are connected to the signal contacts. The first and second signal conductors may have substantial portions extending above the front surfaces of the respective first and second microelectronic devices. The rear surface of the first microelectronic device may be spaced a predetermined first distance above and extend at least generally parallel to the substantial portions of the second signal conductors, such that a desired impedance is achieved for the second signal conductors and empty spaces are defined between the first and second microelectronic devices. The method may further include injecting dielectric material into the empty spaces between the first and second microelectronic devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1E are sectional views illustrating stages in a method of fabricating a microelectronic assembly, in accordance with an embodiment of the invention.

FIG. 2A is a plan view of a microelectronic assembly, in accordance with another embodiment of the invention.

FIG. 2B is a sectional view of the microelectronic assembly of FIG. 2A at line 2B-2B.

FIG. 2C is a sectional view of the microelectronic assembly of FIG. 2A at line 2C-2C.

FIG. 3 is a schematic depiction of a system according to one embodiment of the invention.

DETAILED DESCRIPTION

A method of fabricating a microelectronic assembly 10, in accordance with an embodiment of the invention, is described with reference to sectional views illustrating respective stages of fabrication in FIGS. 1A-1E. As discussed in detail below, in this example, the microelectronic assembly 10 may include one or more microelectronic devices 12 having conductive interconnections, such as through wire bonds, to an element 14 having an interconnection function. The wire-bonds may be formed using conventional wire-bonding techniques. For explanation purposes, the microelectronic device 12 may be a single “bare”, i.e., unpackaged die, e.g., a semiconductor chip having microelectronic circuitry thereon. In alternative embodiments, the microelectronic device 12 can include a packaged semiconductor die, or other unit including one or more semiconductor dies, each typically having active semiconductor devices thereon.

For ease of reference, directions are stated in this disclosure with reference to a “top” or front, i.e., contact-bearing surface 16, of the microelectronic device 12. Generally, directions referred to as “upward” or “rising from” shall refer to the direction orthogonal and away from the device front surface 16. Directions referred to as “downward” shall refer to the directions orthogonal to the device front surface 16 and opposite the upward direction. The term “above” a reference point shall refer to a point upward of the reference point, and the term “below” a reference point shall refer to a point downward of the reference point. The “top” of any individual element shall refer to the point or points of that element which extend furthest in the upward direction, and the term “bottom” of any element shall refer to the point or points of that element which extend furthest in the downward direction.

Referring to FIG. 1A, the interconnection element 14 may be an element of a package having a plurality of conductive leads or traces 18, and a plurality of signal contacts 20 connected to the leads or traces and arranged generally at first locations for interconnection with a microelectronic device.

In the example illustrated in FIGS. 1A-1E, the contacts 20 can carry signals, i.e., voltages or currents which vary with time and which typically convey information. For example, without limitation, voltages or currents which vary with time and which represent state, change, a measurement, a clock or timing input or a control or feedback input are examples of signals.

As used in this disclosure, a statement that an electrically conductive structure is “exposed at” a surface of a dielectric structure indicates that the electrically conductive structure is available for contact with a theoretical point moving in a direction perpendicular to the surface of the dielectric structure toward the surface of the dielectric structure from outside the dielectric structure. Thus, a conductive structure which is exposed at a surface of a dielectric structure may project from such surface; may be flush with such surface; or may be recessed relative to such surface and exposed through a hole or depression in the dielectric.

In one particular embodiment, the interconnection element 14 may be or may include a “substrate”, e.g., a dielectric element bearing a plurality of traces and bond pads. Without limitation, one particular example of a substrate can be a sheet-like flexible dielectric element, typically made of a polymer, e.g., polyimide, among others, having metal traces and bond pads patterned thereon, the bond pads being exposed at at least one face of the dielectric element.

The microelectronic device 12 includes a rear surface 28 remote from the front surface 16, and opposing edges 30 extending between the front surface 16 and the rear surface 28. In one embodiment, the opposing edges 30 of the device 12 may be spaced about 10 mm from each other, and the spacing between the front surface and rear surface of the device 12, or the thickness of the device 12, may be less than about one micron.

Prior to forming conductive interconnections between the microelectronic device 12 and the interconnection element 14, the contacts 20 are exposed at an outwardly-directed or top face 24 of the interconnection element 14. In addition, the device 12 is mounted on the interconnection element 14 with the rear surface 28 of the device 12 facing the top face 24 of the interconnection element 14.

Referring to FIG. 1A, a wire bond 26 or signal conductor extends from a device contact 32 at a location remote from the edges 30 of the microelectronic device 12, such as from a device contact at a portion of the device 12 located centrally between the edges 30, parallel to or substantially parallel to, the front surface 14 toward one of the edges 30. The wire bond or signal conductor 26 conductively connects a device contact 32 at the front surface 16 of the microelectronic device 12 with a contact 20 exposed at the top surface 24 of the interconnection element 14. Wire bonds 26 can be formed with relatively precise placement and within desirable tolerances such that parallel, closely spaced runs can be achieved. For example, wirebonding equipment available from Kulicke and Soffa can be used to achieve precision wire bonds. See, for example, U.S. application Ser. No. 12/722,799, filed Mar. 12, 2010, incorporated by reference herein.

In one embodiment, the signal conductor 26 may be insulated using a dielectric material, for example, by dispensing dielectric material over the signal conductor 26 and thereafter curing the material to form an encapsulant on the signal conductor 26.

Referring to FIG. 1B, a support element 34 having a top surface 36 can be formed above the signal conductors 26. The support element 34 can extend from the top surface 24 of the interconnection element 14. The top surface 36 extends at least substantially parallel to the runs of the signal conductors 26 above the front surface 16 and can extend substantially parallel to the front surface 16 of the device 12. The support element 34 desirably leaves at least some of the contacts 20 on the interconnection element 14 exposed beyond edges 37 of the support element 34 which are adjacent to the edges 30 of the device 12. In one embodiment, the support element 34 can include dielectric material, and may be formed so as to encapsulate the signal conductors 26 connected to the contacts 32 at the front surface 16 of the device 12.

Referring to FIG. 1C, a microelectronic device 12A may be mounted over the top surface 36 of the support element 34 using a layer of adhesive 38, so the devices 12, 12A are arranged on top of each other in the form of a stack. Signal conductors 26A can then be formed using wire bonds, similarly as described above for the device 12, to connect signal contacts 20 on the interconnection element 14 to device contacts 32A on the top surface 16A of the device 12A. The adhesive 38 may be of the type and applied as described, for example, in U.S. Pat. Nos. 5,980,663 and 6,646,289, incorporated by reference herein.

The device 12A may be mounted such that a conductive or semiconducting rear surface 28A of the device 12A extends at least generally parallel to substantial portions of respective lengths of the signal conductors 26 which extend above the front surface 16 of the underlying device 12. In addition, the device 12A may be mounted so that the rear surface 28A is spaced a predetermined distance D1 from the signal conductors 26 connected to the underlying device 12, in order to achieve a selected characteristic impedance for the signal conductors 26. In this way, the rear surface 28A of the device 12A serves as a reference conductor or conductive plane to the signal conductors 26, thereby forming transmission lines which include the respective signal conductors and the device rear surface 28A. The properties of the metal used in the signal conductors 26, the shape and thicknesses of the wires that form the signal conductors 26 and the spacing between the rear surface 28A of the device 12A and the signal conductors 26, contribute to provide a desired characteristic impedance for the signal conductors 26. In one embodiment, these factors and the separation distance D1 may be selected to achieve a characteristic impedance of about 50 ohms for the signal conductors. In another embodiment, these factors may be selected in relation to the distance D1, which may be selected to be about 30-70 microns, to achieve a characteristic impedance of about 50 ohms for the signal conductors.

Based on the geometry of the assembly 10, the characteristic impedance Z₀, in ohms, for the signal conductors connected to the microelectronic device 12 varies in relation to the separation distance D1 between the signal conductors 26 and the rear surface 28A of the microelectronic device 12A. The characteristic impedance Z₀ may be determined using the equation:

${Z_{0} = {\frac{138 \times {\log \left( {4{H/d}} \right)}}{\sqrt{ɛ_{R}}}{ohms}}},$

where H is the separation distance between the signal conductors 26 and the conductive plane defined by the device 12A, d is the diameter of the wire and ∈_(R) is the permeability of the space between the conductors 26 and the device 12A, where the space includes the dielectric material of the support element 34 separating the conductors (wire) 26 from the conductive plane defined by the device 12A. See U.S. application Ser. No. 12/722,799, filed Mar. 12, 2010, incorporated by reference herein, for a detailed discussion of determining characteristic impedance for wirebond signal conductors in a microelectronic assembly having a geometry similar to that of the assembly 10.

In one embodiment, the device 12A may be arranged such that the rear surface 28A extends generally parallel to portions of the signal conductors 26 which extend above the front surface 16 of the device 12 and have lengths of at least one millimeter. In a further embodiment, the lengths of the portions of the signal conductors 26 above which the rear surface 28A extends are at least twenty-five percent of the total lengths of the respective signal conductors 26.

In one embodiment, a separation distance D2 separates the signal conductors 26 and the front surface 16 of the device 12, and D2 may be equal to or exceed D1. The separation distance D2 between the device 12 and its signal conductors 26 desirably is greater than the separation distance D1 between the signal conductors 26 and the overlying device 12A, which serves as a reference conductor for the signal conductors 26. In this way, the arrangement between the signal conductors 26 and the device 12A contributes more to the characteristic impedance for the signal conductors 26 than the arrangement of the signal conductors 26 relative to the device 12. In one embodiment, D2 may exceed D1 by at least about 25 microns.

Referring to FIG. 1D, a support element 34A may be formed over the conductors 26A of the device 12A, similarly as described above for the support element 34, and then a reference conductive element may be formed on the support element 34A. The reference conductive element can be a sheet-like dielectric element 40 having one or more conductive features thereon, such as a conductive plane or a plurality of spaced conductive strips. Alternatively, referring to FIG. 1E, the reference conductive element can be a metal sheet 56.

In a particular embodiment, referring to FIG. 1D, the reference conductive element may be in the form of a substrate including silicon material, such as used to form a microelectronic device, and the substrate 40 may be attached to top surface 36A of the support element 34A using a layer of adhesive 38A. The reference conductive element 40 is spaced a separation distance D3 from the conductors 26A. In this way, the reference conductive element 40 serves as a conductive plane of transmission lines which include the respective conductors 26A to achieve a desired characteristic impedance thereon. Advantageously, in the assembly 10 according to the present invention, each of the device 12A and the reference conductive element 40 functions as an independent or so-called floating conductive plane, to achieve a desired impedance for the signal conductors connected to and running across the top surface of the adjacent, underlying microelectronic device.

In one embodiment, the conductors 26A desirably are spaced a separation distance D4 from the device 12A, where D4 exceeds D3. In alternative embodiments, D1 and D3 may or may not be equal, and D2 and D4 may or may not be equal.

Referring to FIGS. 1D-1E, an encapsulant layer 50 of dielectric material may be formed to encapsulate the reference conductive element and the underlying microelectronic devices 12 in the stack.

In another embodiment, referring to FIG. 1E, the device 12A may include a layer of metal 60 at the rear surface 28A. The metal layer 60 may be laminated to the device 12A, or formed on the device 12A by sputtering, deposition, lamination or the like. Typically, the metal layer is continuous and covers at least substantially all of the rear surface 28A. However, the metal layer may extend on only portions of the rear surface 28A, or may include openings to permit other conductors to contact specific parts of the device 12A. The metal layer may have a thickness from about 100 angstroms to about 100 microns. When the metal layer is formed by sputtering or a chemical or physical vapor deposition process, the thickness can range from about 100 angstroms to about 5 microns. When the metal layer is formed by other means, for example, by plating or as a metal sheet laminated to the surface of the microelectronic device, the thickness can range from about 5 microns to about 100 microns. The thickness of the metal layer 60 may be a substantially small percentage of the entire thickness of the device 12A, such as up to about 50% of the thickness of the entire thickness of the device 12A, because the portion of the device 12A other than the metal layer 60 typically has conductive properties that contribute significantly to the characteristic impedance that may be achieved for the signal conductors 26.

It is to be understood that a microelectronic assembly, in accordance with the present invention, may have more than two microelectronic devices arranged in a stack, for example, up to sixteen or more microelectronic devices. In such assembly, a reference conductive element may be supported a predetermined separation distance above the signal conductors connected to the top microelectronic device in the stack to achieve a desired impedance for the signal conductors connected to the top device, and one or more microelectronic device of the stack may be supported a predetermined distance above the signal conductors connected to the respective adjacent, underlying microelectronic device to achieve respective desired impedances for the signal conductors connected to the adjacent, underlying microelectronic devices.

FIG. 2A is a plan view from above of a microelectronic assembly 100, in accordance with another embodiment of the present invention, before a reference conductor is arranged over wirebond signal conductors 26 that run over the top surface of a microelectronic device 12, which is mounted to an interconnection element 14. The assembly 100 includes elements arranged in a construction similar to the construction of the assembly 10, and like reference numerals designate the same or similar elements. FIG. 2B is a sectional view of the assembly 100, at cross-sectional line 2B-2B as shown in FIG. 2A, following fabrication steps that provide that the microelectronic device 12A, which includes a metal layer 60 at the rear surface 28A, is supported over the device 12 and the reference conductive element 56 is supported over the device 12A. Referring to FIGS. 2A-2B, the assembly 100 may include spacer elements 120 extending vertically between adjacent microelectronic devices in the stack, and vertically between the top microelectronic device in the stack and the reference conductive element overlying the top device, so as to space the reference conductive element a precise separation distance from the signal conductors connected to the top device and also to space the top device 12A a precise separation distance from the signal conductors connected to the underlying device 12. The spacer elements are typically formed from dielectric material, so as to avoid any contribution by the spacer element to the characteristic impedance for the signal conductors. In an embodiment, the spacer elements may be fabricated similar to that in which standoff walls of lidded image sensor packages can be fabricated, such as described in U.S. Patent Publ. No. 2007/0190747, incorporated by reference herein.

Referring to FIG. 2B, in one embodiment, the device 12A is supported on spacer elements 120, which include a first portion 121 and a second portion 122, and the spacer elements 120 space the rear surface 28A of the device 12A a separation distance D1 from the conductors 26 connected to the device 12. In one embodiment, the spacer elements 120 may extend vertically from the top surface 16 of the device 12 to the rear surface 28A of the device 12A, which is the rear surface of a metal layer 60 formed at the rear surface 28A of the device 12A. The separation distance D1 achieves the desired characteristic impedance for the conductors 26. In addition, the spacer elements 120 are adapted so that a separation distance D2, which is greater than D1, is provided between the conductors 26 and the device 12, to avoid contribution of the device 12 to the characteristic impedance for the conductors 26.

Other than the use of spacer elements to support a microelectronic device or the reference conductive element above an adjacent, underlying microelectronic device, so as to provide a precise separation distance between the signal conductor connected to the underlying device and the above microelectronic device or reference conductive element, the fabrication of the assembly 100 may be substantially the same as described above for the assembly 10 with respect to FIGS. 1A-1E.

The fabrication of the assembly 100 using the spacer elements 120 can result in empty spaces existing between adjacent devices in the stack and between the top device in the stack and the reference conductive element. In one embodiment, when the encapsulant 50 is formed over the reference conductive element and the stack of microelectronic devices, encapsulant material may be injected to fill empty spaces between adjacent microelectronic devices in the stack, and between the reference conductive element and the top microelectronic device in the stack.

In one embodiment, the spacer elements 120 include a first adhesive portion 121 and a second adhesive portion 122. During fabrication of the assembly 100, the device 12 having the first adhesive portion 121 on the top surface 16 is provided, the signal conductors 26 are connected to the device contacts of the device 12 and then the device 12A with the second adhesive portion 122 on the rear surface 28A is arranged over the device 12, such that the first and second portions 121, 122 align with and contact each other. The contacting adhesive portions are then cured to form the spacer element 120, which fixedly spaces the devices 12, 12A from each other, and thus fixedly spaces, with great precision, the signal conductors connected to the device 12 a separation distance D1 from the rear surface 28A of the device 12A.

In one embodiment, the spacer elements 120 may be disposed so that the first and second adhesive portions are respectively below and above the conductors 26. Alternatively, the spacer elements may be disposed outside of the region of the assembly where the conductors 26 run.

In another embodiment, a spacer element may include an intermediate portion 123 formed from dielectric or silicon material. Opposing ends of the intermediate portion 123 may terminate in adhesive portions 121 and 122 that adhesively connect the spacer element, respectively, to the rear surface of the device 12A and the front surface of the adjacent device 12.

In one embodiment, the first portion of the spacer element is a curable adhesive material formed on the front surface of a microelectronic device during manufacture thereof.

In a further embodiment, the first and second portions of the spacer element may include curable adhesive material and be formed respectively on the front and rear surface of a microelectronic device during manufacture thereof. Such microelectronic device may then readily be included in a stack of devices, above another microelectronic device in the stack.

In another embodiment, during fabrication of the microelectronic assembly 100, the spacer element, which may be made entirely of adhesive material, may be formed on the top surface of the microelectronic device that is currently the top device in a stack of microelectronic devices. Then, a microelectronic device or reference conductive element, which is to overlie the current top device in the completely fabricated microelectronic assembly, may be placed on top of the current top device. Curing may then be performed to provide that the adjacent components are secured to each other by the spacer element.

Referring to FIGS. 2A, 2B and 2C, the microelectronic devices of the assembly 100 may include exposed opposing edge surfaces 142 which extend between front and rear surfaces thereof. In addition, the reference conductive element 56 may include exposed opposing edge surfaces 144 extending parallel to or aligned with the exposed edge surfaces 142. In one embodiment, masking or like damming techniques may be utilized when the encapsulant 50 is formed over the reference conductive element 56 and the stack of microelectronic devices, so as to provide that the edge surfaces 142 and 144 remain exposed after formation of the encapsulant 50. The assembly 100 may include a conductive interconnecting element 140 that contacts, and interconnects to one another, the exposed edge surfaces 142 of the devices 12 and the exposed edge surfaces 144 of the reference conductive element 56. The conductive interconnecting element 140 may be an electrically conductive paste or solder, and extend in a direction generally orthogonal to a plane in which the devices 12 and the reference conductive element 56 extend.

In alternative embodiments, the conductive element 140 may be provided in a microelectronic assembly to conductively interconnect the exposed edge surface of the reference conductive element to one or more respective exposed edge surfaces of the devices in the stack, or to conductively interconnect two or more exposed edge surfaces of the devices in the stack.

In a further embodiment, the conductive element 140 may be connected to an exposed reference contact 22 arranged at the top surface 24 of the interconnection element 14. The contact 22 is for interconnection to another element, such as, for external interconnection to a printed circuit board. Referring to FIG. 2C, the contact 22 may be connected to a conductive trace extending through the thickness of the element 14 and terminating at a contact at the rear surface of the interconnection element 14, where a connection may be made to a solder bump 160 of a substrate assembly 170 on which the interconnection element 14 is mounted. The assembly 170 may, for example, be a printed circuit board or circuit panel. The solder bump 160 may be connectable with a source of power or ground via a conductive trace in the assembly 170. A connection to ground or a power supply voltage typically provides a reference in a circuit to a voltage which is at least fairly stable with time over frequencies of interest to the operation of the circuit. By connecting the conductor planes of the assembly 100, namely, the devices 12, 12A and the reference conductive element 56, to a reference, a transmission line structure may be achieved which has a beneficial characteristic impedance, because the devices 12 and the reference conductive element 56 of the assembly 100 are at the same potential. The reference conductive element and the devices 12, thus, may function as reference conductors having a fixed potential, such that the characteristic impedances achieved for the signal conductors of the respective devices 12 of the assembly 100 may be maintained at a relatively constant value.

In a further embodiment of the assembly 100 in which the reference conductive element 56 and the devices 12, 12A are not electrically interconnected to one another at their respective exposed edge surfaces, one or more wire bonds 70 may extend from the reference conductive element 56 and connect to a contact on the interconnection element 14. In turn, the interconnection element 14 can be connected to a reference potential, such as through further interconnection between a terminal of the interconnection element 14 and a circuit panel.

The foregoing embodiments have been described with respect to the interconnection of individual microelectronic devices, e.g., semiconductor chips. However, it is contemplated that the methods described herein may be employed in a wafer-scale manufacturing process applied simultaneously to a plurality of chips connected together at edges of the chips, such as a plurality of chips connected together at edges in form of a unit, panel, wafer or portion of a wafer.

The structures discussed above can be utilized in construction of diverse electronic systems. For example, a system 900 in accordance with a further embodiment of the invention includes a structure 906, such as the microelectronic assemblies 10 and 100 described above, in conjunction with other electronic components 908 and 910. In the example depicted, component 908 is a semiconductor chip whereas component 910 is a display screen, but any other components can be used. Of course, although only two additional components are depicted in FIG. 3 for clarity of illustration, the system may include any number of such components. The structure 906 as described above may be, for example, a composite chip or a structure incorporating plural chips. In a further variant, both may be provided, and any number of such structures may be used. Structure 906 and components 908 and 910 are mounted in a common housing 901, schematically depicted in broken lines, and are electrically interconnected with one another as necessary to form the desired circuit. In the exemplary system shown, the system includes a circuit panel 902 such as a flexible printed circuit board, and the circuit panel includes numerous conductors 904, of which only one is depicted in FIG. 3, interconnecting the components with one another. However, this is merely exemplary; any suitable structure for making electrical connections can be used. The housing 901 is depicted as a portable housing of the type usable, for example, in a cellular telephone or personal digital assistant, and screen 910 is exposed at the surface of the housing. Where structure 906 includes a light-sensitive element such as an imaging chip, a lens 911 or other optical device also may be provided for routing light to the structure. Again, the simplified system shown in FIG. 3 is merely exemplary; other systems, including systems commonly regarded as fixed structures, such as desktop computers, routers and the like can be made using the structures discussed above.

While the above description makes reference to illustrative embodiments for particular applications, it should be understood that the claimed invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope of the appended claims. 

1. A method of fabricating a microelectronic assembly comprising: arranging a plurality of microelectronic devices in a stack including a first microelectronic device mounted above an adjacent second microelectronic device, wherein the first and second microelectronic devices in the stack have device contacts exposed at a front surface and have a rear surface remote from the front surface; and connecting the device contacts of the first and second devices with signal contacts of an interconnection element underlying the second microelectronic device using respective first and second signal conductors, the second signal conductors being connected to the signal contacts before the first signal conductors are connected to the signal contacts, the first and second signal conductors having substantial portions extending above the front surfaces of the respective first and second microelectronic devices, and wherein the rear surface of the first microelectronic device is spaced a predetermined first distance above and extends at least generally parallel to the substantial portions of the second signal conductors, such that a desired impedance is achieved for the second signal conductors.
 2. The method of claim 1, wherein the rear surface of the first device extends at least generally parallel to respective lengths of the substantial portions that are at least one millimeter.
 3. The method of claim 1, wherein the rear surface of the first device extends at least generally parallel to respective lengths of the substantial portions that are at least 25% of the total lengths of the respective second signal conductors.
 4. The method of claim 1, wherein a distance between the second signal conductors and the rear surface of the first microelectronic device is equal to or smaller than a distance between the second signal conductors and the front surface of the second microelectronic device.
 5. The method of claim 1, wherein the first device is supported on a support element which spaces the rear surface of the first device above the second signal conductors by the predetermined first distance.
 6. The method of claim 5, wherein the support element is in contact with the interconnection element.
 7. The method of claim 5, wherein the support element is in contact with the front surface of the second microelectronic device.
 8. The method of claim 5, wherein the support element includes a first portion including adhesive material and contacting the front surface of the second microelectronic device and a second portion including adhesive material and contacting the rear surface of the first microelectronic device.
 9. The method of claim 8 further comprising: providing the first portion of the support element on the front surface of the second microelectronic device before connecting the second signal conductors to the device contacts of the second microelectronic device; and connecting the second portion of the support element with the first portion of the support element after connecting the second signal conductors to the device contacts of the second microelectronic device.
 10. The method of claim 9, wherein the support element includes a third portion disposed between the first and second portions.
 11. The method of claim 10, wherein the third portion includes at least one of silicon and polyimide.
 12. The method of claim 5, wherein the support element extends between the first and second microelectronic devices in the stack.
 13. The method of claim 1, wherein each of the first and second devices includes an exposed edge surface extending between the front and rear surfaces thereof, the method further comprising: conductively interconnecting the respective exposed edge surfaces of the first and second microelectronic devices.
 14. The method of claim 13 further comprising: conductively interconnecting the conductively interconnected exposed edge surfaces of the first and second microelectronic devices in the stack with a reference contact of the interconnection element connectable to a source of reference potential.
 15. The method of claim 13 further comprising: applying a conductive paste to conductively interconnect the respective exposed edge surfaces of the first and second microelectronic devices in the stack.
 16. The method of claim 1, wherein a layer of metal is at the rear surface of the first microelectronic device.
 17. The method of claim 1 further comprising: supporting a reference conductive element above the stack, wherein the reference conductive element has a rear surface spaced a predetermined second distance above the runs of the first signal conductors, such that a desired impedance is achieved for the first signal conductors.
 18. The method of claim 17 further comprising: connecting the reference conductive element to a reference contact of the interconnection element connectable to a source of reference potential, using a conductor.
 19. The method of claim 1, wherein the arranging further comprises: providing the second microelectronic device mounted above a third microelectronic device of the stack or the interconnection element; forming an encapsulant layer covering at least a portion of the second microelectronic device and portions of the second signal conductors after connecting the second signal conductors to the signal contacts of the interconnection element; and mounting the first microelectronic device above the encapsulant layer.
 20. The method of claim 1, wherein each of the first and second devices has a first edge remote from a second edge, and wherein at least one of the device contacts of the first and second devices to which the first and second signal conductors are respectively connected is disposed centrally between the first and second remote edges of the respective device.
 21. A method of fabricating a microelectronic assembly comprising: arranging a plurality of microelectronic devices in a stack over an interconnection element, wherein adjacent first and second microelectronic devices in the stack have device contacts exposed at a front surface and have a rear surface remote from the front surface, wherein the interconnection element underlies the second microelectronic device, wherein the device contacts of the first and second devices are connected with signal contacts of the interconnection element by respective first and second signal conductors, the second signal conductors being connected to the signal contacts before the first signal conductors are connected to the signal contacts, the first and second signal conductors having substantial portions extending above the front surfaces of the respective first and second microelectronic devices, wherein the rear surface of the first microelectronic device is spaced a predetermined first distance above and extends at least generally parallel to the substantial portions of the second signal conductors, such that a desired impedance is achieved for the second signal conductors and empty spaces are defined between the first and second microelectronic devices; and injecting dielectric material into the empty spaces between the first and second microelectronic devices.
 22. The method of claim 21, wherein the arranging includes spacing the rear surface of the first device above the second signal conductors by the predetermined first distance with a spacer element that extends between the rear surface of the first device and the front surface of the second device.
 23. The method of claim 21, wherein the rear surface of the first device extends at least generally parallel to respective lengths of the substantial portions that are at least one millimeter.
 24. The method of claim 21, wherein the rear surface of the first device extends at least generally parallel to respective lengths of the substantial portions that are at least 25% of the total lengths of the respective second signal conductors.
 25. The method of claim 21, wherein a distance between the second signal conductors and the rear surface of the first microelectronic device is equal to or smaller than a distance between the second signal conductors and the front surface of the second microelectronic device. 